Verification Planning

Verification planning in ASIC design is a central component of the development process and includes the following activities:

• Requirements analysis: Deriving the verification goals from the design specifications and functional requirements.
• Define verification strategy: Decision on methodology (e.g., simulation, formal verification, emulation) and selection of suitable tools and frameworks (e.g., UVM).
• Planning the testbench architecture: Defining the structure of the test environment (e.g., stimulus generator, monitor, checker) and defining abstraction levels (RTL, SystemVerilog, etc.).
• Test case planning: Identification of relevant scenarios, corner cases and functional coverage (coverage-guided planning), including regression tests.
• Time and resource planning: Estimating the effort required, planning milestones, and coordinating with design and verification teams.
• Define coverage goals: Establish functional, code, and assertion coverage to measure verification progress.
• Risk assessment: Analysis of potential weaknesses in the design and planning of targeted verification tests.
• Documentation and review: Creating the verification plan (vPlan) and coordinating with stakeholders.

The goal of verification planning is to systematically ensure that the design functions correctly before it goes into physical implementation.