Verification

Together with notable clients from the semi-conductor industry, El Camino started some time ago with coverage driven/constraint random verification. Since 2000, we have been a Verification Alliance partner , and to date we have applied or introduced this methodology in numerous projects and trained more than 100 verification engineers in this area.

Whether open or universal verification methodology (OVM/UVM), or metric driven verification (MDV), El Camino is the right partner for the application in the following areas:

  • Virtual prototype
  • HW simulation/acceleration/emulation
  • FPGA prototype
  • HW/SW co-verification
  • Embedded software
  • Including extremely complex systems, such as that of a UMTS base station

When designing verification IP, we generally use the universal verification methodology (UVM) standard. In addition, we also offer formal verification in the areas of HW design, as well as traditional directed tests. Our engineers, who specialize in embedded software tests, are ISTQB® certified.

El Camino’s verification department offers extensive know-how in the following methods and languages:

  • Methods
    • Open/Universal Verification Methodology (OVM/UVM)
    • Metric Driven Verification (MDV)
    • Assertion based verification
    • Formal verification
    • Directed tests
  • Languages
    • e Language/System Verilog
    • SystemC/C++/C
    • Verilog/VHDL
    • PSL, System Verilog Assertions