IP Cores
| Function | Implementation | Description | Datasheet |
|---|---|---|---|
| SD Bus Core | Encrypted or Verilog, NIOS HAL driver |
SD Host Controller (ver. 2.0), SOPC Builder Ready, incl. reference design, optional FAT12/FAT16/FAT32 stand-alone file system |  |
| SD/MMC SPI Core |
Encrypted or VHDL, NIOS HAL driver |
IP for MMC/SD memory card access e.g. from NIOS II, incl. reference design, optional FAT12/FAT16/FAT32 stand-alone file system | |
| SD/MMC Loader | Encrypted (VHDL/Verilog on request) |
IP for the configuration of Altera FPGAs from SD/MMC memory cards | |
| e8254 | Verilog | Synchronous Timer based on Intel 82C54 Programmable Interval Timer | |
